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quad, 12-/14-/16-bit nano dacs with 5 ppm/c on-chip reference, i 2 c interface data sheet ad5625r / ad5645r / ad5665r , ad5625 / ad5665 rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2007-2013 analog devices, inc. all rights reserved. technical support www.analog.com features low power, smallest pin-compatible, quad nano dacs ad5625r/ad5645r/ad5665r 12-/14-/16-bit nanodacs on-chip, 2.5 v, 5 ppm/c reference in tssop on-chip, 2.5 v, 10 ppm/c reference in lfcsp on-chip, 1.25 v, 10 ppm/c reference in lfcsp ad5625/ad5665 12-/16-bit nanodacs external reference only 3 mm 3 mm, 10-lead lfcsp; 14-lead tssop; and 1.665 mm 2.245 mm, 12-ball wlcsp 2.7 v to 5.5 v power supply guaranteed monotonic by design power-on reset to zero scale/midscale per channel power-down hardware ldac and clr functions i 2 c-compatible serial interface supports standard (100 khz), fast (400 khz), and high speed (3.4 mhz) modes applications process control data acquisition systems portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators general description the ad5625r/ad5645r/ad5665r and ad5625/ad5665 members of the nano dac? family are low power, quad, 12-/ 14-/16-bit, buffered voltage-out dacs with/without an on-chip reference. all devices operate from a single 2.7 v to 5.5 v supply, are guaranteed monotonic by design, and have an i 2 c-compatible serial interface. the ad5625r/ad5645r/ad5665r have an on-chip reference. the lfcsp versions of the ad56x5r have a 1.25 v or 2.5 v, 10 ppm/c reference, giving a full-scale output range of 2.5 v or 5 v; the tssop versions of the ad56x5r have a 2.5 v, 5 ppm/c refer- ence, giving a full-scale output range of 5 v. the wlcsp package has a 1.25 v reference. the on-chip reference is off at power-up, allowing the use of an external reference. the internal reference is enabled via a software write. the ad5625/ad5665 require an external reference voltage to set the output range of the dac. the part incorporates a power-on reset circuit that ensures that the dac output powers up to 0 v (por = gnd) or midscale (por = v dd ) and remains there until a valid write occurs. the on-chip precision output amplifier enables rail-to-rail output swing. functional block diagrams figure 1. ad5625r/ad5645r/ad5665r figure 2. ad5625/ad5665 the ad56x5r/ad56x5 use a 2-wire i 2 c-compatible serial interface that operates in stan dard (100 khz), fast (400 khz), and high speed (3.4 mhz) modes. table 1. related devices part no. description ad5025 / ad5045 / ad5065 dual 12-/14-/16-bit dacs ad5624r / ad5644r / ad5664r , ad5624 / ad5664 quad spi 12-/14-/16-bit dacs, with/without internal reference ad5627r / ad5647r / ad5667r , ad5627 / ad5667 dual i 2 c 12-/14-/16-bit dacs, with/without internal reference ad5666 quad spi 16-bit dac with internal reference interface logic sda scl a ddr1 a ddr2 v dd gnd 1.25v/2.5v ref v refin / v refout ad5625r/ad5645r/ad5665r input register dac register string dac a v out a buffer ldac clr por input register dac register string dac b v out b buffer input register dac register string dac c v out c buffer input register dac register string dac d v out d buffer notes 1. the following pins are available only on 14-lead package: addr2, ldac, clr, por. 06341-001 power-on reset power-down logic 0 6341-002 interface logic sda scl addr1 addr2 v dd gnd v refin ad5625/ad5665 input register dac register string dac a v out a buffer ldac clr por input register dac register string dac b v out b buffer input register dac register string dac c v out c buffer input register dac register string dac d v out d buffer notes 1. the following pins are available only on 14-lead package: addr2, ldac, clr, por. power-on reset power-down logic
ad5625r/ad5645r/ad5665r , ad5625/ad5665 data sheet rev. c | page 2 of 36 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagrams ............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? specificationsad5665r/ad5645r/ad5625r ..................... 3 ? specificationsad5665/ad5625 ............................................. 5 ? ac characteristics ........................................................................ 7 ? i 2 c timing specifications ............................................................ 8 ? absolute maximum ratings .......................................................... 10 ? esd caution ................................................................................ 10 ? pin configurations and function descriptions ......................... 11 ? typical performance characteristics ........................................... 13 ? terminology .................................................................................... 21 ? theory of operation ...................................................................... 23 ? digital-to-analog converter (dac) ....................................... 23 ? resistor string ............................................................................. 23 ? output amplifier ........................................................................ 23 ? internal reference ...................................................................... 23 ? external reference ..................................................................... 24 ? serial interface ............................................................................ 24 ? write operation.......................................................................... 24 ? read operation........................................................................... 24 ? high speed mode ....................................................................... 26 ? input shift register .................................................................... 26 ? multiple byte operation ............................................................ 26 ? broadcast mode .......................................................................... 28 ? ldac function .......................................................................... 28 ? power-down modes .................................................................. 30 ? power-on reset and software reset ....................................... 31 ? internal reference setup (r versions) .................................... 31 ? applications information .............................................................. 32 ? using a reference as a power supply for the ad56x5r/ad56x5 ..................................................................... 32 ? bipolar operation using the ad56x5r/ad56x5 .................. 32 ? power supply bypassing and grounding ................................ 32 ? outline dimensions ....................................................................... 33 ? ordering guide .......................................................................... 35 ? revision history 3/13rev. b to rev. c added 12-ball wlcsp ...................................................... universal change to features and general description sections ............... 1 changes to reference output (1.25 v), reference tc parameter, table 2 ............................................................................. 4 added ja thermal impedance, wlcsp parameter, table 6 ... 10 added figure 8; renumbered sequentially ................................ 12 added table 8; renumbered sequentially .................................. 12 changes to internal reference section ........................................ 23 changes to serial interface section and table 9 title................ 24 changes to figure 58 and figure 60 captions ............................ 25 updated outline dimensions ....................................................... 33 changes to ordering guide .......................................................... 35 12/09rev. a to rev. b changes to features section, general description section, and table 1 .......................................................................................... 1 changes to table 2 ............................................................................. 3 changes to internal reference section ........................................ 22 updated outline dimensions ....................................................... 32 changes to ordering guide .......................................................... 33 6/09rev. 0 to rev. a changes to features and general description sections .............. 1 changes to table 2 ............................................................................. 3 changes to table 3 ............................................................................. 5 changes to digital-to-analog converter (dac) section, added figure 54 and figure 55, renumbered subsequent figures ..... 22 changes to ordering guide .......................................................... 33 3/07revision 0: initial version
data sheet ad5625r/ad5 645r/ad5665r, ad5625/ad5665 rev. c | page 3 of 36 specifications specifications ad5665r/ad5645r/ad56 25r v dd = 2.7 v to 5.5 v; r l = 2 k? to gnd; c l = 200 pf to gnd; v refin = v dd ; all specifications t min to t max , un less otherwise noted. table 2 . a grade b grade parameter min typ max min typ max unit test conditions/comments 1 static performance 2 ad5665 r resolution 16 bits relative accuracy 8 16 lsb diff erential nonlinearity 1 lsb guaranteed monotonic by design ad 5645r resolution 14 bits relative accuracy 2 4 lsb differential nonlinearity 0.5 lsb guaranteed monotonic by design ad 5625r resolution 12 12 bits relative accuracy 1 4 0.5 1 lsb differential nonlinearity 1 0.25 lsb guaranteed monotonic by design zero - code error 2 10 2 10 mv all 0s loaded to dac register offset error 1 10 1 10 mv full - scale error ? 0.1 0.5 ? 0.1 0.5 % fsr all 1s loaded to dac register gain error 0.1 1.25 0.1 1 % fsr zero - code error drift 2 2 v/c gain temperature coefficient 2.5 2.5 ppm of fsr/c dc power supply rejection ratio ? 100 ? 100 db dac code = midscale; v dd = 5 v 10% dc crosstalk (external reference) 15 15 v due to full - scale output change, r l = 2 k to gnd or v dd 10 10 v/ma due to load current change 8 8 v due to powering down (per channel) dc crosstalk (internal reference) 25 2 5 v due to full - scale output change, r l = 2 k to gnd or v dd 20 20 v/ma due to load current change 10 10 v due to powering down (per channel) output characteristics 3 output voltage range 0 v dd 0 v dd v internal reference disabl ed 0 2 v ref 2 v ref internal reference enabled capacitive load stability 2 2 nf r l = 10 10 nf r l = 2 k dc output impedance 0.5 0.5 short - circuit current 30 30 ma v dd = 5 v power - up time 4 4 s coming out of po wer - down mode; v dd = 5 v reference inputs reference current 210 260 210 260 a v ref = v dd = 5.5 v reference input range 0.75 v dd 0.75 v dd v reference input impedance 26 26 k
ad5625r/ad5645r/ad5665r , ad5625/ad5665 data sheet rev. c | page 4 of 36 a grade b grade parameter min typ max min typ max unit test conditions/comments 1 reference output (1.25 v) output voltage 1.247 1.253 1.247 1.253 v at ambient reference tc 3 10 10 ppm/c tssop and lfcsp packages 15 ppm/c wlcsp package output impedance 7.5 7.5 k reference output (2.5 v) v dd = 4.5 v to 5.5 v output voltage 2.495 2.505 2.495 2.505 v at ambient reference tc 3 10 5 10 ppm/c output impedance 7.5 7.5 k logic inputs (addrx, clr , ldac , por) 3 i in , input current 1 1 a v inl , input low voltage 0.15 v dd 0.15 v dd v v inh , input high voltage 0.85 v dd 0.85 v dd v c in , pin capacitance 2 2 pf v hyst , input hysteresis 0.1 v dd 0.1 v dd v logic inputs (sda, scl) 3 i in , input current 1 1 a v inl , input low voltage 0.3 v dd 0.3 v dd v v inh , input high voltage 0.7 v dd 0.7 v dd v c in , pin capacitance 2 2 pf v hyst , input hysteresis 0.1 v dd 0.1 v dd v high speed mode 0.05 v dd 0.05 v dd v fast mode logic outputs (sda) 3 v ol , output low voltage 0.4 0.4 v i sink = 3 ma 0.6 0.6 v i sink = 6 ma floating-state leakage current 1 1 a floating-state output capacitance 2 2 pf power requirements v dd 2.7 5.5 2.7 5.5 v i dd (normal mode) 4 v ih = v dd , v il = gnd, full-scale loaded v dd = 4.5 v to 5.5 v 1.0 1.16 1.0 1.16 ma internal reference off v dd = 2.7 v to 3.6 v 0.9 1.05 0.9 1.05 ma internal reference off v dd = 4.5 v to 5.5 v 1.9 2.14 1.9 2.14 ma internal reference on v dd = 2.7 v to 3.6 v 1.4 1.59 1.4 1.59 ma internal reference on i dd (all power-down modes) 5 v dd = 2.7 v to 5.5 v 0.48 1 0.48 1 a v ih = v dd , v il = gnd (lfcsp) v dd = 3.6 v to 5.5 v 0.48 1 0.48 1 a v ih = v dd , v il = gnd (tssop) 1 temperature range of a and b grades is ?40c to +105c. 2 linearity calculated using a reduced code range: ad5665r (code 512 to code 65,024), ad 5645r (code 128 to code 16,256), ad5625r (code 32 to code 4064). output unloaded. 3 guaranteed by design and characterization; not production tested. 4 interface inactive. all dacs active. dac outputs unloaded. 5 all dacs powered down. power-down function is not available on 14-lead tssop parts when the part is powered with v dd < 3.6 v.
data sheet ad5625r/ad5 645r/ad5665r, ad5625/ad5665 rev. c | page 5 of 36 specifications ad5665/ad5625 v dd = 2.7 v to 5.5 v; r l = 2 k? to gnd; c l = 200 pf to gnd; v refin = v dd ; all specifications t min to t max , unless otherwise noted. table 3 . b grade parameter min typ max unit test conditions/comments 1 static performance 2 ad5665 resolution 16 bits relative accuracy 8 16 lsb differential nonlinearity 1 lsb guaranteed monotonic by design ad 5625 resolution 12 bits relative accuracy 0.5 1 lsb differential nonlinearity 0.25 lsb guaranteed monotonic by design zero - code error 2 10 mv all 0s loaded to dac register offset error 1 10 mv full - scale error ? 0.1 0.5 % fsr all 1s loaded to dac register gain error 0.1 1 % fsr zero - code error drift 2 v/c gain temperature coefficient 2.5 ppm of fsr/c dc power supply rejection ratio ? 100 db dac code = midscale; v dd = 5 v 10% dc crossta lk (external reference) 15 v due to full - scale output change, r l = 2 k to gnd or v dd 10 v/ma due to load current change 8 v due to powering down (per channel) dc crosstalk (internal reference) 25 v due to full - scale output change, r l = 2 k to gnd or v dd 20 v/ma due to load current change 10 v due to powering down (per channel) output characteristics 3 output voltage range 0 v dd v capacitive load stability 2 nf r l = 10 nf r l = 2 k dc output impedance 0.5 short - circuit current 30 ma v dd = 5 v power - up time 4 s coming out of power - down mode; v dd = 5 v reference inputs reference current 210 260 a v ref = v dd = 5.5 v reference input range 0.75 v dd v reference input impedance 26 k logic inputs (addrx, clr , ldac , por) 3 i in , input current 1 a v inl , input low voltage 0.15 v dd v v inh , input high voltage 0.85 v dd v c in , pin c apacitance 2 pf v hyst , input hysteresis 0.1 v dd v logic inputs (sda, scl) 3 i in , input current 1 a v inl , input low voltage 0.3 v dd v v inh , input high voltage 0.7 v dd v c in , p in capacitance 2 pf v hyst , input hysteresis 0.1 v dd v high speed mode 0.05 v dd v fast mode
ad5625r/ad5645r/ad5665r, ad5625/ad5665 data sheet rev. c | page 6 of 36 b grade parameter min typ max unit test conditions/comments 1 logic outputs (sda) 3 v ol , output low voltage 0.4 v i sink = 3 ma 0.6 v i sink = 6 ma floating - state leakage current 1 a floating - state output capacitance 2 pf power requirements v dd 2.7 5.5 v i dd (normal mode) 4 v ih = v dd , v il = gnd, full - scale loaded v dd = 4.5 v to 5.5 v 1.0 1.16 ma v dd = 2.7 v to 3.6 v 0.9 1.05 ma i dd (all power - down modes) 5 v dd = 2.7 v to 5.5 v 0.48 1 a v ih = v dd , v il = gnd (lfcsp) v dd = 3.6 v to 5.5 v 0.48 1 a v ih = v dd , v il = gnd (tssop) 1 temperature range of b grade is ?40c to +105c. 2 linearity calculated usi ng a reduced code range: ad5665 (code 512 to code 65,024), ad5625 (code 32 to code 4064). output unloaded. 3 guarantee d by design and characterization; not production tested. 4 in terface inactive. all dacs active. dac outputs unloaded. 5 all dacs powered down. power - down function is not available on 14 - lead tssop parts when the part is powered with v dd < 3.6 v.
data sheet ad5625r/ad5 645r/ad5665r, ad5625/ad5665 rev. c | page 7 of 36 ac characteristics v dd = 2.7 v to 5.5 v; r l = 2 k? to gnd; c l = 200 pf to gnd; v refin = v dd ; all specifications t min to t max , unless otherwise noted. table 4 . parameter 1 , 2 min typ max unit test conditions/comments 3 output voltage settling time ad 5625 r/ad 5625 3 4.5 s ? to ? scale settling to 0.5 lsb ad 5645 r 3.5 5 s ? to ? scale settling to 0.5 lsb ad 5665 r/ad 5665 4 7 s ? to ? scale settling to 2 lsb slew rate 1.8 v/s digital - to - analog glitch impulse 1 lsb change around major carry 15 nv - s lfcsp 5 nv - s tssop digital feedthrough 0.1 nv - s reference feedthrough ? 90 db v ref = 2 v 0.1 v p - p, frequency 10 hz to 20 mhz digital crosstalk 0.1 nv - s analog crosstalk 1 nv - s external reference 4 nv - s internal reference dac - to - dac crosstalk 1 nv - s external reference 4 nv - s internal reference multiplyin g bandwidth 340 khz v ref = 2 v 0.1 v p - p total harmonic distortion ? 80 db v ref = 2 v 0.1 v p - p, frequency = 10 khz output noise spectral density 120 nv/ hz dac code = midscale, 1 khz 100 nv/ hz dac code = midscale, 10 khz output noise 15 v p -p 0.1 hz to 10 hz 1 guarantee d by design and characterization; not production tested. 2 s ee the terminology section. 3 temperature ran ge is ?40c to +105c, typical @ 25c.
ad5625r/ad5645r/ad5665r, ad5625/ad5665 data sheet rev. c | page 8 of 36 i 2 c t iming s pecifications v dd = 2.7 v to 5.5 v; all specifications t min to t max , f scl = 3.4 mhz, unless otherwise noted. 1 table 5 . parameter test conditions 2 min max unit description f scl 3 standard mode 100 k hz serial clock frequency fast mode 400 k hz high speed mode, c b = 100 pf 3.4 mhz high speed mode, c b = 400 pf 1.7 mhz t 1 standard mode 4 s t high , scl high time fast mode 0.6 s high speed mode, c b = 100 pf 60 ns high speed mode, c b = 400 pf 120 ns t 2 standard mode 4.7 s t low , scl low time fast mode 1.3 s high speed mode, c b = 100 pf 160 ns high speed mode, c b = 40 0 pf 320 ns t 3 standard mode 250 ns t su;dat , data setup time fast mode 100 ns high speed mode 10 ns t 4 standard mode 0 3.45 s t hd;dat , data hold time fast mode 0 0.9 s high speed mode, c b = 100 pf 0 70 ns high speed mode, c b = 400 p f 0 150 ns t 5 standard mode 4.7 s t su;sta , set up time for a repeated start condition fast mode 0.6 s high speed mode 160 ns t 6 standard mode 4 s t hd;sta , hold time (repeated) start condition fast mode 0.6 s high speed mode 160 ns t 7 standard mode 4.7 s t buf , bus - free time betwe en a stop and a start condition fast mode 1.3 s t 8 standard mode 4 s t su;sto , setup time for a stop condition fast mode 0.6 s high speed mode 160 ns t 9 standard mode 1000 ns t rda , rise time of sda signal fast mode 300 ns high speed mode, c b = 100 pf 10 80 ns high speed mode, c b = 400 pf 20 160 ns t 10 standard mode 300 ns t fda , fall time of sda s ignal fast mode 300 ns high speed mode, c b = 100 pf 10 80 ns high sp eed mode, c b = 400 pf 20 160 ns t 11 standard mode 1000 ns t rcl , rise time of scl signal fast mode 300 ns high speed mode, c b = 100 pf 10 40 ns high speed mode, c b = 400 pf 20 80 ns t 11a standard mode 1000 ns t rcl1 , rise time of scl signal af ter a repeated start conditi on and after an acknowledge bit fast mode 300 ns high speed mode, c b = 100 pf 10 80 ns high speed mode, c b = 4 00 pf 20 160 ns
data sheet ad5625r/ad5 645r/ad5665r, ad5625/ad5665 rev. c | page 9 of 36 parameter test conditions 2 min max unit description t 12 standard mode 300 ns t fcl , fall time of scl signal fast mode 300 ns high speed mode, c b = 100 pf 10 40 ns high speed mode, c b = 400 pf 20 80 ns t 13 standard mode 10 ns ldac pulse width low fast mode 10 ns high speed mode 10 ns t 14 standard mode 300 ns falling edge of ninth scl clock pulse of l ast byte of a valid write to ldac falling edge fast mode 300 ns high speed mode 30 ns t 15 standard mode 20 ns clr pulse width low fast mode 20 ns high speed mode 20 ns t s p 4 fast mode 0 50 ns pulse widt h of spike suppressed high speed mode 0 10 ns 1 see figure 3 . high speed mode timing specification applies only to the ad5625rbruz - 2/ad5625rbruz - 2reel7 and ad5665rbruz - 2/ad5665rbruz - 2reel7. 2 c b refers to the capacitance on the bus line. 3 the sda and scl timing is measured with the input filters enabled. switching off the input filters improves the transfer rate but has a negative effect on the emc behavior of the part. 4 input filtering on the scl and sda inputs suppresses noise spikes that a re less than 50 ns for fast mode or less than 10 ns for high speed mode. figure 3. 2- wire serial interface timing diagram scl sda p s s p t 8 t 6 t 5 t 3 t 10 t 9 t 4 t 6 t 1 t 2 t 11 t 12 t 14 clr t 13 t 15 ldac* t 7 *asynchronous ldac update mode. 06341-003
ad5625r/ad5645r/ad5665r, ad5625/ad5665 data sheet rev. c | page 10 of 36 absolute maximum rat ings t a = 25 c, unless otherwise noted. table 6 . parameter rating v dd to gnd ? 0.3 v to + 7 v v out to gnd ?0.3 v to v dd + 0.3 v v refin /v refout to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v operating temperature range , industrial ?40c to +105c storage temperature range ? 65 c to + 150 c juncti on temperature (t j max imum ) 150 c power dissipation (t j max ? t a )/ ja ja thermal impedance lfcsp_wd (4 - layer board) 61 c/w tssop 150.4c/w wlcsp 75 c/w reflow soldering peak temperature , rohs c ompliant 260c 5c stresses above those listed un der absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
data sheet ad5625r/ad5 645r/ad5665r, ad5625/ad5665 rev. c | page 11 of 36 pin configuration s and function descrip tions figure 4 . pin configuration (14 - lead tssop), r suffix version figure 5 . pin configuration (14 - lead tssop) figure 6 . pin configuration (10 - lead lfcsp ), r suffix version figure 7 . pin configuration (10 - lead lfcsp ) table 7 . pin function descriptions pin number 14- lead 10- lead mnemonic description 1 n/a ldac pulsing this pin low allows any or all dac registers to be updated if the input registers have new data. this allows simultaneous update of all dac outputs. alternatively, this pin can be tied permanently low. 2 n/a addr1 three -s tate a ddress i nput. sets the two least significant bits (bit a1, bit a0) of the 7 - bit slave address (see table 10) . 3 9 v dd power s upply i nput. these parts can be operated from 2.7 v to 5.5 v, and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 4 1 v out a analog o utput voltage from dac a . the output amplifier has rail -to - rail operation. 5 4 v out c analog o utput v oltage from dac c . the output amplifier has rail -to - rail operation. 6 n/a por power -o n r eset p in. tying the por pin to gnd powers up the part to 0 v. tying the por pin to v dd powers up the part to midscale. 7 10 v refin /v refout t he ad56x5r ha ve a common pin for reference input and reference output. when using the internal reference, this is the reference output pin. when using an external reference, this is the reference input pin. the default for this pin is as a reference input. ( the internal reference and reference output are only available on r suffix versions.) the ad56x 5 has a reference input pin only. 8 n/a addr2 three -s tate address i nput. sets b it a3 and bit a2 of the 7 - bit slave address (see table 10). 9 n/a clr asynchronous clear i nput. the clr input is fa lling - edge sensitive. while clr is low, all ldac pulses are ignored. when clr is activated, zero scale is loaded to all input and dac registers. this clears the output to 0 v. the part exits clear code mode on the falling edge of the ninth clock pulse of the last byte of the valid write. if clr is activated during a write sequence, the wr ite is aborted. if clr is activated during high speed mode , the part exi ts high speed mode. 10 5 v out d analog o utput v oltage from dac d . the output amplifier has rail -to - rail operation. 11 2 v out b analog o utput v oltage from dac b. the o utput amplifier has rail - to - rail operation. 12 3 gnd ground r eference point for a ll c ircuitry on the p art. 13 8 sda serial data l ine. this is used in conjunction with the scl line to clock data into or out of the 16 - bit input register. it is a bidirectio nal, open - drain data line that should be pulled to the supply with an external pull - up resistor. 14 7 scl serial clock l ine. this is used in conjunction with the sda line to clock data into or out of the 16 - bit input register. n/a 6 addr three -s tate a ddr ess i nput. sets the two least significant bits (bit a1, bit a0) of the 7 - bit slave address (see table 9 ) . epad for the 10 - lead lfcsp , the exposed pad must be tied to gnd. 1 ldac 14 scl 2 addr1 13 sda 3 v dd 12 gnd 4 v out a 11 v out b 5 v out c 10 v out d 6 por 9 clr 7 v refin /v refout 8 addr2 ad5625r/ ad5645r/ ad5665r top view (not to scale) 06341-120 1 ldac 14 scl 2 addr1 13 sda 3 v dd 12 gnd 4 v out a 11 v out b 5 v out c 10 v out d 6 por 9 clr 7 v refin 8 addr2 ad5625/ ad5665 top view (not to scale) 06341-121 1 v out a 10 v refin /v refout 2 v out b 9 v dd 3 gnd 8 sda 4 v out c 7 scl 5 v out d 6 addr ad5625r/ ad5645r/ ad5665r top view (not to scale) exposed pad tied to gnd. 06341-122 1 v out a 10 v refin 2 v out b 9 v dd 3 gnd 8 sda 4 v out c 7 scl 5 v out d 6 addr ad5625/ ad5665 top view (not to scale) exposed pad tied to gnd. 06341-123
ad5625r/ad5645r/ad5665r, ad5625/ad5665 data sheet rev. c | page 12 of 36 figure 8. pin configuration (1 2 - ball wlcsp ) table 8 . pin function descriptions pin no. mnemonic description a1 v ref in /v refout the ad5665r has a common pin for reference input and reference output. when using the internal reference, this is the reference output pin. when using an external reference, this is the reference input pin. the default for this pin is as a reference input. a2, b2, c2 gnd ground reference point for all circuitry on the part. a3 v out a analog output voltage from dac a. the output amplifier has rail -to - rail operation. b1 v dd power supply input. the ad5665r can be operated from 2.7 v to 5.5 v, and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. b3 v out b analog output voltage from dac b. the output amplifier has rail -to - rail operation. c1 sda serial data lin e. this is used in conjunction with the scl line to clock data into or out of the 16 - bit input register. it is a bidirectional, open - drain data line that should be pulled to the supply with an external pull- up resistor. c3 v out c analog output voltage from dac c. the output amplifier has rail -to - rail operation. d1 scl serial clock line. this is used in conjunction with the sda line to clock data into or out of the 16 - bit input register. d2 addr three - state address input. sets the two least significant bit s (bit a1, bit a0) of the 7 - bit slave address (see table 9 ). d3 v out d analog output voltage from dac d. the output amplifier has rail -to - rail operation. t op view (bal l side down) not to scale gnd v out a vdd gnd v out b sda gnd v out c scl addr v out d 1 a b c d 2 3 bal l a1 indic a t or 06341-108 v refin / v refout
data sheet ad5625r/ad5 645r/ad5665r, ad5625/ad5665 rev. c | page 13 of 36 typical performance characteristics figure 9. inl, ad5665 , external reference figure 10 . inl, ad5645 r , external reference figure 11 . inl, ad5625 , external reference figure 12 . dnl, ad5665 , e xternal reference figure 13 . dnl, ad5645 r , external reference figure 14 . dnl, ad5625 , external reference code inl error (lsb) 10 4 6 8 0 2 ?6 ?10 ?8 ?2 ?4 0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k v dd = v ref = 5v t a = 25c 06341-005 code inl error (lsb) 4 ?4 0 2500 5000 7500 10000 12500 15000 ?3 ?2 ?1 0 1 2 3 v dd = v ref = 5v t a = 25c 06341-006 code inl error (lsb) 1.0 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4000 ?0.8 ?0.6 ?0.4 0 0.4 0.2 ?0.2 0.6 0.8 v dd = v ref = 5v t a = 25c 06341-100 code dn l error (lsb) 1.0 0.6 0.4 0.2 0.8 0 ?0.4 ?0.2 ?0.6 ?1.0 ?0.8 0 10k 20k 30k 40k 50k 60k v dd = v ref = 5v t a = 25c 06341-007 dn l error (lsb) 0.5 0.3 0.2 0.1 0.4 0 ?0.2 ?0.1 ?0.3 ?0.5 ?0.4 v dd = v ref = 5v t a = 25c code 0 2500 5000 7500 10000 12500 15000 06341-008 dn l error (lsb) 0.20 0.10 0.05 0.15 0 ?0.05 ?0.10 ?0.20 ?0.15 code 0 500 1000 1500 2000 2500 3000 3500 4000 v dd = v ref = 5v t a = 25c 06341-009
ad5625r/ad5645r/ad5665r, ad5625/ad5665 data sheet rev. c | page 14 of 36 figure 15 . inl, ad5665r , 2.5 v internal reference figure 16 . inl, ad5645r , 2.5 v internal reference figure 17 . inl, ad5625r , 2. 5 v internal reference figure 18 . dnl, ad5665r , 2.5 v internal reference figure 19 . dnl, ad5645r , 2.5 v internal reference figure 20 . dnl, ad5625r , 2.5 v internal reference code in l error (lsb) 10 8 0 ?10 ?6 ?8 ?4 6 ?2 4 2 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v dd = 5v v refout = 2.5v t a = 25c 06341-010 c o d e in l error (lsb) 4 3 ? 4 ? 3 ? 2 2 ? 1 1 0 16250 15000 13750 12500 1 1250 10000 8750 7500 6250 5000 3750 2500 1250 0 v d d = 5 v v r e f o u t = 2 . 5 v t a = 2 5 c 06341-011 c o d e inl error (lsb) 1 . 0 0 . 8 0 ? 1 . 0 ? 0 . 8 ? 0 . 6 0 . 6 ? 0 . 4 ? 0 . 2 0 . 4 0 . 2 0 10 0 0 5 0 0 20 0 0 15 0 0 35 0 0 30 0 0 25 0 0 40 0 0 v d d = 5 v v r e f o u t = 2 . 5 v t a = 2 5 c 06341-012 c o d e dn l error (lsb) 1 . 0 0 . 8 0 ? 1 . 0 ? 0 . 6 ? 0 . 8 ? 0 . 4 0 . 6 ? 0 . 2 0 . 4 0 . 2 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v d d = 5 v v r e f o u t = 2 . 5 v t a = 2 5 c 06341-013 code dn l error (lsb) 0.5 0.4 0 ?0.5 ?0.3 ?0.4 ?0.2 0.3 ?0.1 0.2 0.1 16250 15000 13750 12500 1 1250 10000 8750 7500 6250 5000 3750 2500 1250 0 v dd = 5v v refout = 2.5v t a = 25c 06341-014 code dn l error (lsb) 0.20 0.15 0 ?0.20 ?0.15 ?0.10 0.10 ?0.05 0.05 0 1000 500 2000 1500 3500 3000 2500 4000 v dd = 5v v refout = 2.5v t a = 25c 06341-015
data sheet ad5625r/ad5 645r/ad5665r, ad5625/ad5665 rev. c | page 15 of 36 figure 21 . inl, ad5665r ,1.25 v internal reference figure 22 . inl, ad5645 r , 1.25 v internal reference figure 23 . inl, ad5625r ,1.25 v internal reference figure 24 . dnl, ad5665r ,1.25 v internal reference figure 25 . dnl, ad5645r ,1.25 v internal reference figure 26 . dnl, ad5625r , 1.25 v internal reference code inl error (lsb) 10 8 4 6 2 0 ?4 ?2 ?6 ?8 ?10 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v dd = 3v v refout = 1.25v t a = 25c 06341-016 code inl error (lsb) 4 ?4 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 3 2 1 0 ?1 ?2 ?3 v dd = 3v v refout = 1.25v t a = 25c 06341-017 code inl error (lsb) 1.0 ?1.0 0 500 1000 1500 2000 2500 3000 3500 4000 0 0.8 0.6 0.4 0.2 ?0.2 ?0.4 ?0.6 ?0.8 v dd = 3v v refout = 1.25v t a = 25c 06341-018 code dnl error (lsb) 1.0 0.8 0.4 0.6 0.2 0 ?0.4 ?0.2 ?0.6 ?0.8 ?1.0 65000 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 v dd = 3v v refout = 1.25v t a = 25c 06341-019 code dnl error (lsb) 0.5 ?0.5 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 0 0.4 0.3 0.2 0.1 ?0.1 ?0.2 ?0.3 ?0.4 v dd = 3v v refout = 1.25v t a = 25c 06341-020 code dnl error (lsb) 0.20 ?0.20 0 500 1000 1500 2000 2500 3000 3500 4000 0 0.15 0.10 0.05 ?0.05 ?0.10 ?0.15 v dd = 3v v refout = 1.25v t a = 25c 06341-021
ad5625r/ad5645r/ad5665r , ad5625/ad5665 data sheet rev. c | page 16 of 36 figure 27. inl error and dnl error vs. temperature figure 28. inl error and dnl error vs. v ref figure 29. inl error and dnl error vs. supply figure 30. gain error and full-scale error vs. temperature figure 31. zero-scale error and offset error vs. temperature figure 32. gain error and full-scale error vs. supply temperature (c) error (lsb) 8 6 4 2 ?6 ?4 ?2 0 ?8 ?40 ?20 40 200 100 80 60 min dnl max dnl max inl min inl v dd = v ref = 5v 06341-022 v ref (v) error (lsb) 10 4 6 8 2 0 ?8 ?6 ?4 ?2 ?10 0.75 1.25 1.75 2.25 4.25 3.75 3.25 2.75 4.75 min dnl max dnl max inl min inl v dd = 5v t a = 25c 06341-023 v dd (v) error (lsb) 8 6 4 2 ?6 ?4 ?2 0 ?8 2.7 3.2 3.7 4.7 4.2 5.2 min dnl max dnl max inl min inl t a = 25c 06341-024 temperature (c) error (% fsr) 0 ?0.04 ?0.02 ?0.06 ?0.08 ?0.10 ?0.18 ?0.16 ?0.14 ?0.12 ?0.20 ?40 ?20 40 200 100 80 60 v dd = 5v gain error full-scale error 06341-025 temperature (c) error (mv) 1.5 1.0 0.5 0 ?2.0 ?1.5 ?1.0 ?0.5 ?2.5 ?40 ?20 40 20 08 0 60 100 offset error zero-scale error 06341-026 v dd (v) error (% fsr) 1.0 ?1.5 ?1.0 ?0.5 0 0.5 ?2.0 2.7 3.2 3.7 4.7 4.2 5.2 gain error full-scale error 06341-027
data sheet ad5625r/ad5 645r/ad5665r, ad5625/ad5665 rev. c | page 17 of 36 figure 33 . zero - scale error and offset error vs. supply figure 34 . i dd histogram with external reference figure 35 . i dd histogram with internal reference figure 36 . supply current vs. dac code figure 37 . supply current vs. supply figure 38 . supply current vs. tempe rature v dd (v) error (mv) 1.0 0.5 0 ?2.0 ?1.5 ?1.0 ?0.5 ?2.5 2.7 3.2 4.2 3.7 5.2 4.7 zero-scale error offset error t a = 25c 06341-028 i dd (ma) number of devices 0 30 25 20 15 10 5 0.88 0.89 0.90 0.91 0.92 0.93 0.94 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 v dd = 3.6v v dd = 5.5v 06341-029 i dd (ma) number of devices 0 25 20 15 10 5 1.35 1.37 1.39 1.41 1.43 1.45 1.47 1.49 1.51 1.53 1.55 1.57 1.59 1.61 1.63 1.65 1.67 1.69 1.71 1.73 1.75 1.77 1.79 1.81 1.83 1.85 1.87 1.89 1.91 1.93 1.99 1.95 1.97 v dd = 3.6v v dd = 5.5v 06341-030 v refout = 1.25v v refout = 2.5v code i dd (ma) 0 2.0 1.6 1.8 1.4 1.2 1.0 0.8 0.6 0.4 0.2 512 10512 20512 30512 40512 50512 60512 t a = 25c v dd = 5.5v v refout = 2.5v v refin = 5v 06341-060 v dd (v) i dd (ma) 0 0.2 0.4 0.8 0.6 1.0 1.2 3.2 2.7 3.7 4.2 4.7 5.2 t a = 25 c 06341-061 temperature (c) i dd (ma) 1.2 0.2 0.4 1.0 0.6 0.8 0 ?40 ?20 0 20 40 60 80 100 06341-063 v dd = v ref = 5v v dd = v ref = 3v
ad5625r/ad5645r/ad5665r, ad5625/ad5665 data sheet rev. c | page 18 of 36 figure 39 . headroom at rails vs. source and sink figure 40 . ad56x5r with 2.5 v reference, source and sink capability figure 41 . ad56x5r with 1.25 v reference, s ource and sink capability figure 42 . full - scale settling time, 5 v figure 43 . power - on reset to 0 v figure 44 . exiting power - down to midscale current (ma) error vo lt age (v) 0.5 0.4 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 ?10 ?8 ?6 ?4 ?2 0 2 4 8 6 10 v dd = 3v v refout = 1.25v v dd = 5v v refout = 2.5v dac loaded with zero-scale sinking current dac loaded with full-scale sourcing current 06341-031 current (ma) v out (v) 6 5 4 3 2 1 ?1 0 ?30 ?20 ?10 0 10 20 30 v dd = 5v v refout = 2.5v t a = 25c zero scale ful l scale midscale 1/4 scale 3/4 scale 06341-046 current (ma) v out (v) 4 ?1 0 1 2 3 ?30 ?20 ?10 0 10 20 30 v dd = 3v v refout = 1.25v t a = 25c zero scale ful l scale midscale 1/4 scale 3/4 scale 06341-047 time base = 4s/div v dd = v ref = 5v t a = 25 c full-scale code change 0x0000 to 0xffff output loaded with 2k? and 200pf to gnd v out = 909mv/div 1 06341-048 ch1 2.0v ch2 500mv m100s 125ms/s a ch1 1.28v 8.0ns/pt v dd = v ref = 5v t a = 25 c v out v dd 1 2 max(c2) 420.0mv 06341-049 v dd = 5v sync slck v out 1 3 ch1 5.0v ch3 5.0v ch2 500mv m400ns a ch1 1.4v 2 06341-050
data sheet ad5625r/ad5 645r/ad5665r, ad5625/ad5665 rev. c | page 19 of 36 figure 45 . digital - to- analog glitch impulse (negative) figure 46 . analog crosstalk, external reference figure 47 . analog crosstalk, internal reference figure 48 . 0.1 h z to 10 hz output noise plot, external reference figure 49 . 0.1 hz to 10 hz output noise plot, 2.5 v internal reference figure 50 . 0.1 hz to 10 hz output noise plot, 1.25 v internal reference sample number v out (v) 2.521 2.522 2.523 2.524 2.525 2.526 2.527 2.528 2.529 2.530 2.531 2.532 2.533 2.534 2.535 2.536 2.537 2.538 0 50 100 150 350 400 200 250 300 450 512 v dd = v ref = 5v t a = 25 c 5ns/sample number glitch impulse = 9.494nv 1lsb change around midscale (0x8000 to 0x7fff) 06341-058 sample number v out (v) 2.491 2.492 2.493 2.494 2.495 2.496 2.497 2.498 0 50 100 150 350 400 200 250 300 450 512 v dd = v ref = 5v t a = 25 c 5ns/sample number analog crosstalk = 0.424nv 06341-059 sample number v out (v) 2.456 2.458 2.460 2.462 2.464 2.466 2.468 2.470 2.472 2.474 2.476 2.478 2.480 2.482 2.484 2.486 2.488 2.490 2.492 2.494 2.496 0 50 100 150 350 400 200 250 300 450 512 v dd = 5v v refout = 2.5v t a = 25 c 5ns/sample number analog crosstalk = 4.462nv 06341-062 1 v dd = v ref = 5v t a = 25 c dac loaded with midscale 4s/div 2v/div 06341-051 5s/div 10v/div 1 v dd = 5v v refout = 2.5v t a = 25 c dac loaded with midscale 06341-052 4s/div 5v/div 1 v dd = 3v v refout = 1.25v t a = 25 c dac loaded with midscale 06341-053
ad5625r/ad5645r/ad5665r, ad5625/ad5665 data sheet rev. c | page 20 of 36 f igure 51 . noise spectral density, internal reference figure 52 . total harmonic distortion figure 53 . settling time vs. capacitive load figure 54 . multiplying bandwidth frequenc y (hz) output noise (nv/hz) 800 0 100 200 300 400 500 600 700 100 10k 1k 100k 1m v dd = 3v v refout = 1.25v v dd = 5v v refout = 2.5v t a = 25c midscale loaded 06341-054 frequency (hz) thd (db) ?20 ?50 ?80 ?30 ?40 ?60 ?70 ?90 ?100 2k 4k 6k 8k 10k v dd = 5v t a = 25c dac loaded with full scale v ref = 2v 0.3v p-p 06341-055 ca p aci t ance (nf) time (s) 16 14 12 10 8 6 4 0 1 2 3 4 5 6 7 9 8 10 v ref = v dd t a = 25c v dd = 5v v dd = 3v 06341-056 frequency (hz) bandwidth (db) 5 ?40 10k 100k 1m 10m ? 35 ? 30 ? 25 ? 20 ? 15 ? 10 ? 5 0 v dd = 5v t a = 25c 06341-057
data sheet ad5625r/ad5 645r/ad5665r, ad5625/ad5665 rev. c | page 21 of 36 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in lsbs, from a straight line passing through the endpoints o f the dac transfer function. differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensure s monotonicity. this dac is guaranteed monotonic by design. zero - code error zero - code error is a measurement of the output error when zero scale (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero - code error is always posi tive in the ad5665r because the output of the dac cannot go below 0 v due to a combination of the offset errors in the dac and the out - put amplifier. zero - code error is expressed in millivolts ( mv ) . full - scale error full - scale error is a measurement of the output error when full - scale code (0xffff) is loaded to the dac register. ideally, the output should be v dd ? 1 lsb. full - scale error is expressed as a percentage of full - scale range (fsr) . gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from ideal expressed as a percentage of full - scale range ( fsr ) . zero - code error drift zero - code error drift is a measurement of the change in zero - code error with a change in temperature. it is expressed in microvolts per degrees celsius ( v/c ) . gain temperature coefficient gain temperature coe fficient is a measurement of the change in gain error with changes in temperature. it is expressed in parts per million (ppm) of full - scale range per degrees celsius ( fsr/c ) . offset error offset error is a measure of the difference between v out (actual) and v out (ideal) expressed in mv in the linear region of the transfer function. offset error is measured on the ad5665r with code 512 loaded in the dac register. it can be negative or positive. dc power supply rejection ratio (psrr) dc psrr indicates how t he output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to the change in v dd for full - scale output of the dac. it is measured in decibels ( db ) . v ref is held at 2 v, and v dd is varied by 10% . output volta ge settling time output voltage settling time is the amount of time it takes for the output of a dac to settle to a specified level for a ? to ? full - scale input change, and it is measured from the rising edge of the stop condition. digital -to - analog glitc h impulse digital - to - analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv - s and is measured when the digital input code is chang ed by 1 lsb at the major carry transition (0x7fff to 0x8000) (see figure 45). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs o f the dac but is measured when the dac output is not u pdated. it is specified in nv - s and is measured with a full - scale code change on the data bus, that is, from all 0 s to all 1 s and vice versa. reference feedthrough reference feedthrough is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated. it is expressed in decibels ( db ) . output noise spectral density output noise spectral density is a measurement of the internally generated rando m noise , which is characterized as a spectral density ( nanovolts per square roo t of hertz frequency ( nv/hz) ) . it is measured by loading the dac to midscale and measuring noise at the output. it is measured in nanovolts per square root of hertz frequency ( nv/hz ) . a plot of noise spectral density is shown in f igure 51. dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full - scale output change on one dac (or soft power - down and power - up) while monitoring another dac kept at midscale. it is expressed in microvolts ( v ) . dc crosstalk due to load current change is a measure of the impact that a change in load current on one dac has on another dac kept at midscale. it is expressed in microvolts per milliampere ( v/ma ) . digital crosstalk this is the glitch impulse trans ferred to the output of one dac at midscale in response to a full - scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nanovolts per second ( nv - s) .
ad5625r/ad5645r/ad5665r, ad5625/ad5665 data sheet rev. c | page 22 of 36 analog crosstalk analog crosstalk is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full - scale code change (al l 0s to all 1s and vice versa) and then executi ng a software ldac and monitor ing the output of the dac whose digital code was not changed. the area of the glitch is expressed in nanovolts per second ( nv - s) . dac -to - dac crosstalk dac - to - dac crosstalk is the glitch impulse transferred to the output of o ne dac due to a digital code change and subsequent analog output change of another dac. it is measured by loading the attack channel with a full - scale code change (all 0s to all 1s and vice versa) with ldac low while monitoring the output of the victim channel that is at midscale. the energy of the glitch is expressed in nanovolts per second ( nv - s) . multiplying bandwidth the multiplying bandwidth is a measure of the finite bandwidth of the amplifiers within the dac. a sine wave on the ref erence (with full - scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) thd is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measurement of the harmonics present on the dac output. it is measured in decibels ( db ) .
data sheet ad5625r/ad5645r/ad5665r , ad5625/ad5665 rev. c | page 23 of 36 theory of operation digital-to-analog converter (dac) the ad56x5r/ad56x5 dacs are fabricated on a cmos process. the ad56x5 does not have an internal reference, and the dac architecture is shown in figure 55. the ad56x5r does have an internal reference and can be configured for use with either an internal or external reference (see figure 55 and figure 56). because the input coding to the dac is straight binary, the ideal output voltage when using an external reference is given by ? ? ? ? ? ? ?? n refin out d vv 2 figure 55. internal configuration when using an external reference the ideal output voltage when using the internal reference is given by ? ? ? ? ? ? ??? n refout out d v v 2 2 where: d is the decimal equivalent of the binary code that is loaded to the dac register, as follows: 0 to 4095 for ad5625r/ad5625 (12-bit). 0 to 16,383 for ad5645r (14-bit). 0 to 65,535 for ad5665r/ad5665 (16-bit). n is the dac resolution. figure 56. internal configuration when using the internal reference resistor string the resistor string is shown in figure 57. it is simply a string of resistors, each of value r. the code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. output amplifier the output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 v to v dd . it can drive a load of 2 k in parallel with 1000 pf to gnd. the source and sink capabilities of the output amplifier are shown in figure 39 and figure 40. the slew rate is 1.8 v/s with a ? to ? full-scale settling time of 7 s. figure 57. resistor string internal reference the ad5625r/ad5645r/ad5665r feat ure an on-chip reference. versions without the r suffix require an external reference. the on-chip reference is off at power-up and is enabled via a write to a control register. see the internal reference setup section for details. versions packaged in a 10-lead lfcsp have a 1.25 v reference or a 2.5 v reference, giving a full-scale output of 2.5 v or 5 v, depending on the model selected (see the ordering guide). the wlcsp package has an internal reference of 1.25 v. these parts can be operated with a v dd supply of 2.7 v to 5.5 v. versions packaged in a 14-lead tssop have a 2.5 v reference, giving a full-scale output of 5 v. parts are functional with a v dd supply of 2.7 v to 5.5 v, but with a v dd supply of less than 5 v, the output is clamped to v dd . see the ordering guide for a full list of models. the internal reference associated with each part is available at the v refout pin (available on r suffix versions only). a buffer is required if the reference output is used to drive external loads. when using the internal reference, it is recom- mended that a 100 nf capacitor be placed between the reference output and gnd for reference stability. ref buffer output amplifier gain = 2 dac register v refin /v refout v out 06341-034 gnd ref (+) ref (?) resistor string output amplifier gain = 2 dac register ref (+) v refin /v refout v out ref (?) resistor string gnd 06341-035 1.25v internal reference 1 1 can be overdriven by v refin /v refout . r r r r r to output amplifier 0 6341-033
ad5625r/ad5645r/ad5665r, ad5625/ad5665 data sheet rev. c | page 24 of 36 external r eference the v refin pin on the ad56x5r allows the use of an external reference if the applicatio n requires it. the default condition of the on - chip reference is off at power - up. all devices can be operated from a single 2.7 v to 5.5 v supply. serial interface the ad56x5r/ad56x5 have 2 - wire i 2 c - compatible serial inter - faces. the ad56x5r/ad56x5 can be connected to an i 2 c bus as a slave device, under the control of a master device. see figure 3 for a timing diagr am of a typical write sequence. the ad56x5r/ad56x5 support standard (100 khz), fast (400 khz), and hig h speed (3.4 mhz) data transfer modes. high speed operation is only available on selected models. see the order ing guide for a full list of models. support is not provided for 10 - bit addressing and general call ad dressing. the ad56x5r/ad56x5 each has a 7 - bit slave address. the 10- lead and 12 - ball versions of the part have a slave address whose five msbs are 00011, and the two lsbs are set by the state of the addr address pin, which determines the state of the a0 a nd a1 address bits. the 14- lead versions of the part have a slave address whose three msbs are 001, and the four lsbs are set by the addr1 and addr2 address pins, which determine the state of the a0 and a1 and a2 and a3 address bits , respectively. the faci lity to make hardwired changes to the addr pin allows the user to incorporate up to three of these devices on one bus, as outlined in table 9 . table 9 . addr pin settings (10 - lead and 12 - ball p ackage s ) addr p in c onnection a1 a0 v dd 0 0 n c 1 0 gnd 1 1 the facility to make hardwired changes to the addr1 and the addr2 pins allows the user to incorporate up to nine of these devices on one bus, as outlined in table 10. table 10. addr1, addr2 pin setting s (14 - lead package) addr2 pin connection addr1 pin connection a3 a2 a1 a0 v dd v dd 0 0 0 0 v dd nc 0 0 1 0 v dd gnd 0 0 1 1 nc v dd 1 0 0 0 nc nc 1 0 1 0 nc gnd 1 0 1 1 gnd v dd 1 1 0 0 gnd nc 1 1 1 0 gnd gnd 1 1 1 1 the 2 - wire serial bu s protocol operates as follows: 1. the master initiates data transfer by establishing a start condition when a high - to - low transition on the sda line occurs while scl is high. the following byte is the address byte, which consists of the 7 - bit slave address. the slave address corresponding to the transmitted address responds by pulling sda low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its shift register. 2. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the s da line must occur during the low period of scl and remain stable during the high period of scl. 3. when all data bits have been read or written, a stop condition is established. in write mode, the master pulls the sda line high during the 10 th clock pulse t o establish a stop condition. in read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the sda line remains high). the master brings the sda line low before the 10 th clock pulse, and then high during the 10 th clock pulse to esta blish a stop condition. w rite operation when writing to the ad56x5r/ad56x5 , the user must begin with a start command followed by an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. the ad5665 requires two bytes of data for the dac and a command byte that controls various dac functions. three bytes of data must , therefore , be written to the dac, the command byte followed by the most significant data byte and the least signifi cant data byte, as shown in figure 58 and figure 59. after these data bytes are acknowledged by the ad56x5r/ad56x5 , a stop condition follows. r ead o peration when reading da ta back from the ad56 x 5r/ad56 x 5 , the user begins with a start command followed by an address byte (r/ w = 1), after which the dac acknowledges that it is prepared to transmit data by pulling sda low. two bytes of data are then read from the dac, which are both acknowledged by the master as shown in figure 60 and figure 61 . a stop condition follows.
data sheet ad5625r/ad5 645r/ad5665r, ad5625/ad5665 rev. c | page 25 of 36 figure 58 . i 2 c write operation (10 - lead and 12 - ball package s) figure 59 . i 2 c write operation (14 - lead package) figure 60 . i 2 c read operation (10 - lead and 12 - ball package s) frame 2 command byte frame 1 slave address 1 9 9 1 scl start by master ack. by ad56x5 ack. by ad56x5 sda r/w db23 a0 a1 1 0 0 0 1 db22 db21 db20 db19 db18 db17 db16 1 9 9 1 ack. by ad56x5 ack. by ad56x5 frame 4 least significant data byte frame 3 most significant data byte stop by master scl (continued) sda (continued) db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 06341-103 frame 2 command byte frame 1 slave address 1 9 9 1 scl start by master ack. by ad56x5 ack. by ad56x5 sda r/w db23 a0 a1 a2 1 0 0 a3 db22 db21 db20 db19 db18 db17 db16 1 9 9 1 ack. by ad56x5 ack. by ad56x5 frame 4 least significant data byte frame 3 most significant data byte stop by master scl (continued) sda (continued) db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 06341-104 frame 2 command byte frame 1 slave address 1 9 9 1 scl start by master ack. by ad56x5 ack. by master sda r/w db23 a0 a1 1 0 0 0 1 db22 db21 db20 db19 db18 db17 db16 1 9 9 1 ack. by master no ack. frame 4 least significant data byte frame 3 most significant data byte stop by master scl (continued) sda (continued) db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 06341-101
ad5625r/ad5645r/ad5665r , ad5625/ad5665 data sheet rev. c | page 26 of 36 figure 61. i 2 c read operation (14-lead package) figure 62. placing the ad56x5rbruz-2/ad56x5rbruz-2reel7 in high speed mode high speed mode some models offer high speed serial communication with a clock frequency of 3.4 mhz. see the ordering guide for a full list of models. high speed mode communication commences after the master addresses all devices connected to the bus with the master code 00001xxx to indicate that a high speed mode transfer is to begin. no device connected to the bus is permitted to acknowl- edge the high speed master code; therefore, the code is followed by a no acknowledge. next, the master must issue a repeated start followed by the device address. the selected device then acknowledges its address. all devices continue to operate in high speed mode until the master issues a stop condition. when the stop condition is issued, the devices return to standard/fast mode. the part also returns to standard/fast mode when clr is activated while the part is in high speed mode. input shift register the input shift register is 24 bits wide. data is loaded into the device as a 24-bit word under the control of a serial clock input, scl. the timing diagram for this operation is shown in figure 3. the eight msbs make up the command byte. db23 is reserved and should always be set to 0 when writing to the device. db22 (s) is used to select multiple byte operation. the next three bits are the command bits (c2, c1, and c0) that control the mode of operation of the device. see table 11 for details. the last three bits of the first byte are the address bits (a2, a1, and a0). see table 12 for details. the rest of the bits are the 16-/14-/12-bit data-word. the data-word comprises the 16-/14-/12-bit input code followed by two or four dont care bits for the ad5645r and the ad5625r/ad5625, respectively (see figure 65 through figure 67). multiple byte operation multiple byte operation is supported on the ad56x5r/ad56x5. a 2-byte operation is useful for applications that require fast dac updating and do not need to change the command byte. the s bit (db22) in the command register can be set to 1 for 2-byte mode of operation (see figure 64). for standard 3-byte and 4-byte operation, the s bit (db22) in the command byte should be set to 0 (see figure 63). frame 2 command byte frame 1 slave address 19 9 1 scl start by master ack. by ad56x5 ack. by master sda r/w db23 a0 a1a2 10 0 a3 db22 db21 db20 db19 db18 db17 db16 19 9 1 ack. by master no ack. frame 4 least significant data byte frame 3 most significant data byte stop by master scl ( continued) sda (continued) db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 6341-102 0 6341-105 scl 00001xxx 001a3a2a1a0r/w sda 1919 no ack. sr start by master ack. by ad56x5 hs-mode master code serial bus address byte fast mode high-speed mode
data sheet ad5625r/ad5 645r/ad5665r, ad5625/ad5665 rev. c | page 27 of 36 figure 63 . multiple block write with command byte in each block (s = 0) figure 64 . multiple block write with initial command byte only (s = 1) figure 65 . ad5665r/ad5665 input shift register (16 - bit dac) figure 66 . ad5645r input shift register (14 - bit dac) figure 67 . ad5625r/ad562 5 input shift register (12 - bit dac) slave address command byte most significant data byte command byte least significant data byte most significant data byte least significant data byte s = 0 block 1 s = 0 block 2 most significant data byte command byte least significant data byte stop s = 0 block n 06341-107 slave address command byte most significant data byte most significant data byte least significant data byte least significant data byte s = 1 block 1 s = 1 block 2 most significant data byte least significant data byte stop s = 1 block n 06341-106 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 r s reserved byte selection c2 c1 c0 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 command dac address dac data dac data command byte data high byte data low byte 06341-108 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 r s reserved byte selection c2 c1 c0 a2 a1 a0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x command dac address dac data dac data command byte data high byte data low byte 06341-109 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 r s reserved byte selection c2 c1 c0 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x command dac address dac data dac data command byte data high byte data low byte 06341-110
ad5625r/ad5645r/ad5665r, ad5625/ad5665 data sheet rev. c | page 28 of 36 broadcast mode broadcast addressing is supported on the ad56x5r/ad56x5 in write mode only . broadcast addressing can be used to synchro - nously update or power down multiple ad56x5r/ad56x5 devices. when the broadcast ad dress is used , the ad56x5r/ ad56x5 respond regardless of the states of the address pins. the ad56x5r/ad56x5 broadcast address is 00010000. table 11 . command definition c2 c1 c0 command 0 0 0 write to input register n 0 0 1 update dac register n 0 1 0 write to input register n, update all (software ldac ) 0 1 1 write to and update dac channel n 1 0 0 power up/power down 1 0 1 reset 1 1 0 ldac register setup 1 1 1 internal reference setup (on /off ) table 12 . dac address command a2 a1 a0 address ( n ) 0 0 0 dac a 0 0 1 dac b 0 1 0 dac c 0 1 1 dac d 1 1 1 all dacs ldac function the ad56x5r/ad56x5 dacs have double - buffered interfaces consi sting of two banks of registers: input registers and dac registers. the input registers are connected directly to the input shift register, and the digital code is transferred to the relevant input register up on completion of a valid write sequence. the dac regist ers contain the digital code used by the resistor strings. access to the dac registers is controlled by the ldac pin. when the ldac pin is high, the dac registers are latched and the input registers can change state wit hout affecting the contents of the dac registers. when ldac is brought low, however, the dac registers become transparent and the contents of the input registers are transferred to them. the double - buffered interface is useful if the user requires simultaneous updating of all dac outputs. the user can write to one of the input registers individually and then, by bringing ldac low when writing to the other dac input register, all outputs update simultaneously. these parts each contain an extra feature whereby a dac register is not updated unless its input register has been updated since the last time ldac was brought low. normally, when ldac is brought low, the dac registers are filled w ith the contents of the input registers. in the case of the ad56x5r/ad56x5 , the dac register updates only if the input register has changed since the last time the dac register was updated, thereby removing unnecessary digital crosstalk. the outputs of all dacs can be simultaneously updated, using the hardware ldac pin. .
data sheet ad5625r/ad5645r/ad5665r , ad5625/ad5665 rev. c | page 29 of 36 synchronous ldac the dac registers are updated after new data is read in. ldac can be permanently low or pulsed. asynchronous ldac the outputs are not updated at the same time that the input registers are written to. when ldac goes low, the dac registers are updated with the contents of the input register. the ldac register gives the user full flexibility and control over the hardware ldac pin (and software ldac on the 10-lead parts that do not have the hardware ldac pinsee table 13). this register allows the user to select which combination of channels to simultaneously update when the hardware ldac pin is executed. setting the ldac bit register to 0 for a dac channel means that the update of this channel is controlled by the ldac pin. if this bit is set to 1, this channel synchronously updates; that is, the dac register is updated after new data is read in, regardless of the state of the ldac pin. the device effectively sees the ldac pin as being pulled low. see table 14 for the ldac register mode of operation. this flexibility is useful in applications when the user wants to simultaneously update select channels while the rest of the channels are synchronously updating. writing to the dac using command 110 loads the 4-bit ldac register [db3:db0]. the default for each channel is 0; that is, the ldac pin works normally. setting the bits to 1 means that the dac register is updated, regardless of the state of the ldac pin. see figure 68 for the contents of the input shift register during the ldac register setup command. table 13. ldac register mode of operation on the 10-lead lfcsp (load dac register) ldac bits (db3 to db0) ldac mode of operation 0 normal operation (default), dac register update is controlled by the write command. 1 the dac registers are updated after new data is read in. table 14. ldac register mode of operation on the 14-lead tssop (load dac register) ldac bits (db3 to db0) ldac pin ldac operation 0 1/0 determined by the ldac pin. 1 x = dont care the dac registers are updated after new data is read in. figure 68. ldac setup command r s c2 c1 c0 a2 a1 a0 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 x reserved don?t care 1 1 0 a2 a1 a0 x x x x x x x x x x x x dac d dac c dac b dac a command dac address (don?t care) don?t care don?t care dac select (0 = ldac pin enabled) 06341-115
ad5625r/ad5645r/ad5665r , ad5625/ad5665 data sheet rev. c | page 30 of 36 power-down modes command 100 is reserved for the power-up/power-down function. the power-up/power-down modes are programmed by setting bit db5 and bit db4. this defines the output state of the dac amplifier, as shown in table 15. bit db3 to bit db0 determine to which dac or dacs the power-up/power-down command is applied. setting one of these bits to 1 applies the power-up/power-down state defined by db5 and db4 to the corresponding dac. if a bit is 0, the state of the dac is unchanged. figure 70 shows the contents of the input shift register for the power-up/power-down command. when bit db5 and bit db4 are set to 0, the part works normally with its normal power consumption of 1 ma at 5 v. however, for the three power-down modes, the supply current falls to 480 na at 5 v. not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this allows the output impedance of the part to be known while the part is in power-down mode. the outputs can either be connected internally to gnd through a 1 k or 100 k resistor or be left open-circuited (three-state) as shown in figure 67. note that the 14-lead tssop models offer the power-down function when the part is operated with a v dd of 3.6 v to 5.5 v. the 10-lead lfcsp models offer the power-down function when the part is powered with a v dd of 2.7 v to 5.5 v. table 15. modes of operation for the ad56x5r/ad56x5 db5 db4 operating mode 0 0 normal operation power-down modes 0 1 1 k pull-down resistor to gnd 1 0 100 k pull-down resistor to gnd 1 1 three-state, high impedance figure 69. output stage during power-down the bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when power-down mode is activated. however, the contents of the dac register are unaffected when in power-down. the time to exit power- down is typically 4 s for v dd = 5 v or v dd = 3 v. figure 70. power-up/power-down command resistor network v out resistor string dac power-down circuitry amplifier 06341-038 r s c2 c1 c0 a2 a1 a0 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 x reserved don?t care 1 0 0 a2 a1 a0 x x x x x x x x x x pd1 pd0 dac d dac c dac b dac a command dac address (don?t care) don?t care don?t care power- down mode dac select (1 = dac selected) 06341-116
data sheet ad5625r/ad5645r/ad5665r , ad5625/ad5665 rev. c | page 31 of 36 power-on reset and software reset the ad56x5r/ad56x5 contain a power-on reset circuit that controls the output voltage during power-up. the 10-lead version of the device powers up to 0 v. the 14-lead version has a power-on reset (por) pin that allows the output voltage to be selected. by connecting the por pin to gnd, the ad56x5r/ ad56x5 output powers up to 0 v; by connecting the por pin to v dd , the ad56x5r/ad56x5 output powers up to midscale. the output remains powered up at this level until a valid write sequence is made to the dac. this is useful in applications where it is important to know the state of the output of the dac while it is in the process of powering up. any events on ldac or clr during power-on reset are ignored. there is also a software reset function. command 101 is the software reset command. the software reset command contains two reset modes that are software programmable by setting bit db0 in the input shift register. table 16 shows how the state of the bit corresponds to the software reset modes of operation of the devices. figure 71 shows the contents of the input shift register during the software reset mode of operation. table 16. software reset modes for the ad56x5r/ad56x5 db0 registers reset to zero 0 dac register input shift register 1 (power-on reset) dac register input shift register ldac register power-down register internal reference setup register internal reference setup (r versions) the on-chip reference is off at power-up by default. it can be turned on by sending the reference setup command (111) and setting db0 in the input shift register. table 17 shows how the state of the bit corresponds to the mode of operation. table 17. reference setup command db0 action 0 internal reference off (default) 1 internal reference on figure 71. reset command figure 72. reference setup command x s c2 c1 c0 a2 a1 a0 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 x reserved don?t care 1 0 1 x x x x x x x x x x x x x x x x x x rst command dac address (don?t care) don?t care don?t care reset mode 06341-113 r s c2 c1 c0 a2 a1 a0 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 x reserved don?t care 1 1 1 x x x x x x x x x x x x x x x x x x ref command dac address (don?t care) don?t care don?t care reference mode 06341-114
ad5625r/ad5645r/ad5665r, ad5625/ad5665 data sheet rev. c | page 32 of 36 application s information using a reference as a power supply for the ad56 x 5r/ad56 x 5 because the supply current required by the ad56x5r/ad56x5 is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the part (see figure 73 ). this is especially useful if the power supply is noisy or if the system supply voltages are at some value other than 5 v or 3 v, for example, 15 v. the voltage reference outputs a steady supply voltage for the ad56x5r/ad56x5 . if the low dropout ref195 is used, it must supply 450 a of current to the ad56x5r/ad56x5 with no load on the output of the dac. when the dac output is loaded, the ref195 also must supply the current to the load. the total current required (with a 5 k? load on the dac output) is 1 m a + (5 v/5 k ) = 2 ma the load regulation of the ref195 is typically 2 ppm/ma, resulting in a 4 ppm ( 20 v) error for the 2 ma current drawn from it. this corresponds to a 0. 263 lsb error. figure 73 . ref195 as power supply to the ad56x5r/ad56x5 bipolar operation us ing the ad56 x 5r/ad56 x 5 the ad56x5r/ad56x5 have been designed for single - supply operation, but a bipolar output range is also possible using the circuit shown in figure 74. the circuit gives an output voltage range of 5 v. r a i l - to - rail operation at the amplifier output is achievable using an ad820 or an op295 as the output amplifier. the output voltage for any input code can be calculated as follows: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = r1 r2 v r1 r2 r1 d v v dd dd o 536 , 65 where d represents the input code in decimal (0 to 65,535). if v dd = 5 v, r1 = r2 = 10 k?, v 5 536 , 65 10 ? ? ? ? ? ? ? = d v o this is an output voltage range of 5 v, w i t h 0 x 0000 corre - sponding to a ?5 v output and 0xffff corresponding to a + 5 v output. figure 74 . bipolar operation with the ad56x5r/ad56x5 power supply by passing and groundin g when accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. the printed circuit board containing the ad56x5r/ad56x5 should have separate analog and digital secti ons, each having its own area of the board. if the ad56x5r/ad56x5 are in a system where other devices require an agnd - to - dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the ad56x5r/ad56x 5 . the power supply to the ad56x5r/ad56x5 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should be located as close as possible to the device, with the 0.1 f capaci - tor ideally right up against the device. the 10 f capacitor is the tantalum bead type. it is important that the 0.1 f capacitor have low effective series resistance (esr) and low effective series inductance (esi), for example, common ceramic types of capacitors. this 0.1 f capacitor provides a low impedance path to grou nd for high frequencies caused by transient currents due to internal logic switching. the power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line. clocks and other fa st switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only , and the signal traces are placed on the solder side. however, this is not always possible with a 2 - layer board. 2-wire serial interface scl sda 5v v out = 0v to 5v v dd gnd 15v ref195 ad5625r/ ad5645r/ ad5665r/ ad5625/ ad5665 06341-043 2-wire serial interface 5 n? +5v ?5v ad820/ op295 ad5625r/ ad5645r/ ad5665r/ ad5625/ ad5665 v dd v out 5 n? 5v v o 0.1f 10f +5v sda scl gnd 06341-044
data sheet ad5625r/ad5645r/ad5665r, ad5625/ad5665 rev. c | page 33 of 36 outline dimensions figure 75 . 10 - lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp - 10 - 9) dimensions shown in millimeters figure 76 . 14 - lead thin shrink small outline package [tssop] (ru - 14) dimensions shown in millimeters 2.48 2.38 2.23 0.50 0.40 0.30 10 1 6 5 0.30 0.25 0.20 pin 1 index are a sea ting plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pa d 3.10 3.00 sq 2.90 pin 1 indic a t or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 02-05-2013-c t op view bottom view 0.20 min compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 se a ting plane
ad5625r/ad5645r/ad5665r, ad5625/ad5665 data sheet rev. c | page 34 of 36 figure 77 . 12 - ball wafer level chip scale package [wlcsp] (cb - 12 - 9) dimensions shown in millimeters a b c d 0.650 0.595 0.540 1.705 1.665 1.625 2.285 2.245 2.205 1 2 3 bot t om view (bal l side up) t op view (bal l side down) end view 0.340 0.320 0.300 1.50 ref 1.00 ref 0.50 bsc bal l a1 identifier 08-31-2012- a sea ting plane 0.270 0.240 0.210 0.380 0.355 0.330 coplanarity 0.05
data sheet ad5625r/ad5645r/ad5665r, ad5625/ad5665 rev. c | page 35 of 36 order ing guide model 1 temperature range accuracy on - chip reference max imum i 2 c speed package description package option branding ad 5625 bcpz -r 2 ? 40 c to + 105 c 1 lsb inl none 400 khz 10 - lead lfcsp_wd cp -10 -9 d 8 v ad 5625 bcpz - reel 7 ? 40 c to + 105 c 1 lsb inl none 400 khz 10 - lead lfcsp_wd cp -10 -9 d 8 v ad 5625 bruz ? 40 c to + 105 c 1 lsb inl none 400 khz 14 - lead tssop ru -14 ad 5625 bruz - reel 7 ? 40c to + 105 c 1 lsb inl none 400 khz 14 - lead tssop ru -14 ad 5625 rbcpz -r 2 ? 40 c to + 105 c 1 lsb inl 1.25 v 400 khz 10 - lead lfcsp_wd cp -10 -9 d 8 s ad 5625 rbcpz - reel 7 ? 40 c to + 105 c 1 lsb inl 1.25 v 400 khz 10 - lead lfcsp_wd cp -10 -9 d 8 s ad 5625 racpz - reel 7 ? 40c to +105c 4 lsb inl 1.25 v 400 khz 10 - lead lfcsp_wd cp -10 -9 deu ad 5625 racpz -1 rl 7 ? 40 c to + 105 c 4 lsb inl 2.5 v 400 khz 10 - lead lfcsp_wd cp -10 -9 dfw ad 5625 rbruz -1 ? 40 c to + 105 c 1 lsb inl 2.5 v 400 khz 14 - lead tssop ru -14 ad 5625 rbruz -1 reel 7 ? 40c to + 105 c 1 lsb inl 2.5 v 400 khz 14 - lead tssop ru -14 ad 5625 rbruz -2 ? 40 c to + 105 c 1 lsb inl 2.5 v 3.4 mhz 14 - lead tssop ru -14 ad 5625 rbruz -2 reel 7 ? 40 c to + 105 c 1 lsb inl 2.5 v 3.4 mhz 14 - lead tssop ru -14 ad 5645 rbcpz -r 2 ? 40 c to + 105 c 4 lsb inl 1.25 v 400 khz 10 - lead lfcsp_wd cp -10 -9 d 89 ad 5645 rbcpz - reel 7 ? 40 c to + 105 c 4 lsb inl 1.25 v 400 khz 10 - lead lfcsp_wd cp -10 -9 d 89 ad 5645 rbruz ? 40 c to + 105 c 4 lsb inl 2.5 v 400 khz 14 - lead tssop ru -14 ad 5645 rbruz - reel 7 ? 40 c to + 105 c 4 lsb inl 2 . 5 v 400 khz 14 - lead tssop ru -14 ad 5665 bcpz -r 2 ? 40 c to + 105 c 16 lsb inl none 400 khz 10 - lead lfcsp_wd cp -10 -9 d 6 u ad 5665 bcpz - reel 7 ? 40 c to + 105 c 16 lsb inl none 400 khz 10 - lead lfcsp_wd cp -10 -9 d 6 u ad 5665 bruz ? 40 c to + 105 c 16 lsb inl none 400 khz 14 - lead tssop ru -14 ad 5665 bruz - reel 7 ? 40 c to + 105 c 16 lsb inl none 400 khz 14 - lead tssop ru -14 ad5665rbcbz -1 -rl7 ? 40 c to + 105 c 16 lsb inl 1.25 v 400 khz 12 - ball wlcsp cb -12 -9 ad 5665 rbcpz -r 2 ? 40 c to + 105 c 16 lsb inl 1.25 v 400 khz 10 - lead lfcsp_wd cp -10 -9 da 2 ad 5665 rbcpz - reel 7 ? 40 c to + 105 c 16 lsb inl 1.25 v 400 khz 10 - lead lfcsp_wd cp -10 -9 da 2 ad 5665 rbruz -1 ? 40 c to + 105 c 16 lsb inl 2.5 v 400 khz 14 - lead tssop ru -14 ad 5665 rbruz -1 reel 7 ? 40 c to + 105 c 16 lsb inl 2.5 v 400 khz 14 - lead tssop ru -14 ad 5665 rbruz -2 ? 40 c to + 105 c 16 lsb inl 2.5 v 3.4 mhz 14 - lead tssop ru -14 ad 5665 rbruz - 2 reel 7 ? 40 c to + 105 c 16 lsb inl 2.5 v 3.4 mhz 14 - lead tssop ru - 14 eval -ad 5665 rebz 1 tssop evaluation board eval -ad 5665 rebz 2 lfcsp ev aluation board 1 z = rohs c ompliant p art .
ad5625r/ad5645r/ad5665r, ad5625/ad5665 data sheet rev. c | page 36 of 36 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2007 - 2013 analog devices, in c. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06341 - 0 - 3/13(c)

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